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MB85R1002A
■ FUNCTIONAL TRUTH TABLE
Mode
CE1
CE2
WE
OE
LB
UB
I/O1 to I/O8
I/O9 to I/O16
Supply
Current
H
X
X
X
X
X
Standby Precharge
X
X
L
X
X
H
X
H
X
X
X
X
Hi-Z
Hi-Z
Standby
(I SB )
X
X
X
X
H
L
H
L
Data Output
Data Output
Read
L
H
H
H
L
L
L
H
L
L
H
L
L
H
Data Output
Hi-Z
Data Output
Data Output
Hi-Z
Data Output
Data Output
Hi-Z
H
L
Hi-Z
Data Output
Read
L
L
Data Output
Data Output
(Pseudo-SRAM,
OE control* 1 )
L
H
H
L
H
H
L
Data Output
Hi-Z
Hi-Z
Data Output
Operation
L
L
Data Input
Data Input
(I CC )
Write
L
H
L
L
H
H
L
H
L
L
H
L
L
H
Data Input
Hi-Z
Data Input
Data Input
Hi-Z
Data Input
Data Input
Hi-Z
H
L
Hi-Z
Data Input
Write
L
L
Data Input
Data Input
(Pseudo-SRAM,
L
H
H
L
H
Data Input
Hi-Z
WE control* 2 )
H
L
Hi-Z
Data Input
Note: L = V IL , H = V IH , X can be either V IL or V IH , Hi-Z = High Impedance
: Latch address and latch data at falling edge,
: Latch address and latch data at rising edge
*1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read.
*2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.
4
DS501-00004-1v0-E
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